/******************************************************
 *
 *	File Name	:	s5p_lcd.h
 *
******************************************************/
#ifndef __S5P_LCD_H__
#define __S5P_LCD_H__

#if 0//defined(CONFIG_SMDKC100)
/* Video Main Control 0 register - VIDCON0 */
#define S3C_VIDCON0_INTERLACE_F_PROGRESSIVE		(0<<29)
#define S3C_VIDCON0_INTERLACE_F_INTERLACE		(1<<29)
#define S3C_VIDCON0_INTERLACE_F_MASK			(1<<29)
#define S3C_VIDCON0_VIDOUT(x)  				(((x)&0x7)<<26)
#define S3C_VIDCON0_VIDOUT_RGB_IF			(0<<26)
#define S3C_VIDCON0_VIDOUT_TV				(1<<26)
#define S3C_VIDCON0_VIDOUT_I80IF0			(2<<26)
#define S3C_VIDCON0_VIDOUT_I80IF1			(3<<26)
#define S3C_VIDCON0_VIDOUT_TVNRGBIF 			(4<<26)
#define S3C_VIDCON0_VIDOUT_TVNI80IF0			(6<<26)
#define S3C_VIDCON0_VIDOUT_TVNI80IF1			(7<<26)
#define S3C_VIDCON0_VIDOUT_MASK				(7<<26)
#define S3C_VIDCON0_L1_DATA16(x)  			(((x)&0x7)<<23)
#define S3C_VIDCON0_L1_DATA16_SUB_16_MODE		(0<<23)
#define S3C_VIDCON0_L1_DATA16_SUB_16PLUS2_MODE		(1<<23)
#define S3C_VIDCON0_L1_DATA16_SUB_9PLUS9_MODE 		(2<<23)
#define S3C_VIDCON0_L1_DATA16_SUB_16PLUS8_MODE		(3<<23)
#define S3C_VIDCON0_L1_DATA16_SUB_18_MODE		(4<<23)
#define S3C_VIDCON0_L0_DATA16(x)  			(((x)&0x7)<<20)
#define S3C_VIDCON0_L0_DATA16_MAIN_16_MODE		(0<<20)
#define S3C_VIDCON0_L0_DATA16_MAIN_16PLUS2_MODE		(1<<20)
#define S3C_VIDCON0_L0_DATA16_MAIN_9PLUS9_MODE		(2<<20)
#define S3C_VIDCON0_L0_DATA16_MAIN_16PLUS8_MODE		(3<<20)
#define S3C_VIDCON0_L0_DATA16_MAIN_18_MODE		(4<<20)
#define S3C_VIDCON0_PNRMODE(x)  			(((x)&0x3)<<17)
#define S3C_VIDCON0_PNRMODE_RGB_P			(0<<17)
#define S3C_VIDCON0_PNRMODE_BGR_P			(1<<17)
#define S3C_VIDCON0_PNRMODE_RGB_S			(2<<17)
#define S3C_VIDCON0_PNRMODE_BGR_S			(3<<17)
#define S3C_VIDCON0_PNRMODE_MASK			(3<<17)
#define S3C_VIDCON0_CLKVALUP_ALWAYS 			(0<<16)
#define S3C_VIDCON0_CLKVALUP_ST_FRM 			(1<<16)
#define S3C_VIDCON0_CLKVAL_F(x)				(((x)&0xFF)<<6)
#define S3C_VIDCON0_VCLKEN_ENABLE			(1<<5)
#define S3C_VIDCON0_CLKDIR_DIVIDED   			(1<<4)
#define S3C_VIDCON0_CLKDIR_DIRECTED  			(0<<4)
#define S3C_VIDCON0_CLKSEL(x)   			(((x)&0x3)<<2)
#define S3C_VIDCON0_CLKSEL_F_HCLK	  		(0<<2)
#define S3C_VIDCON0_ENVID_ENABLE	    		(1 << 1)	/* 0:Disable 1:Enable LCD video output and logic immediatly */
#define S3C_VIDCON0_ENVID_DISABLE	    		(0 << 1)	/* 0:Disable 1:Enable LCD video output and logic immediatly */
#define S3C_VIDCON0_ENVID_F_ENABLE     			(1 << 0)	/* 0:Dis 1:Ena wait until Current frame end. */
#define S3C_VIDCON0_ENVID_F_DISABLE     		(0 << 0)	/* 0:Dis 1:Ena wait until Current frame end. */

/* Video Main Control 1 register - VIDCON1 */
#define S3C_VIDCON1_IVCLK_FALL_EDGE 			(0<<7)
#define S3C_VIDCON1_IVCLK_RISE_EDGE 			(1<<7)
#define S3C_VIDCON1_IHSYNC_NORMAL			(0<<6)
#define S3C_VIDCON1_IHSYNC_INVERT			(1<<6)
#define S3C_VIDCON1_IVSYNC_NORMAL			(0<<5)
#define S3C_VIDCON1_IVSYNC_INVERT			(1<<5)
#define S3C_VIDCON1_IVDEN_NORMAL			(0<<4)
#define S3C_VIDCON1_IVDEN_INVERT			(1<<4)

/* Video Main Control 2 register - VIDCON2 */
#define S3C_VIDCON2_EN601_DISABLE			(0<<23)
#define S3C_VIDCON2_EN601_ENABLE			(1<<23)
#define S3C_VIDCON2_EN601_MASK				(1<<23)
#define S3C_VIDCON2_TVFORMATSEL0_HARDWARE		(0<<14)
#define S3C_VIDCON2_TVFORMATSEL0_SOFTWARE		(1<<14)
#define S3C_VIDCON2_TVFORMATSEL0_MASK			(1<<14)
#define S3C_VIDCON2_TVFORMATSEL1_RGB			(0<<12)
#define S3C_VIDCON2_TVFORMATSEL1_YUV422			(1<<12)
#define S3C_VIDCON2_TVFORMATSEL1_YUV444			(2<<12)
#define S3C_VIDCON2_TVFORMATSEL1_MASK			(0x3<<12)
#define S3C_VIDCON2_ORGYUV_YCBCR			(0<<8)
#define S3C_VIDCON2_ORGYUV_CBCRY			(1<<8)
#define S3C_VIDCON2_ORGYUV_MASK				(1<<8)
#define S3C_VIDCON2_YUVORD_CBCR				(0<<7)
#define S3C_VIDCON2_YUVORD_CRCB				(1<<7)
#define S3C_VIDCON2_YUVORD_MASK				(1<<7)

/* VIDEO Time Control 0 register - VIDTCON0 */
#define S3C_VIDTCON0_VBPDE(x)				(((x)&0xFF)<<24)
#define S3C_VIDTCON0_VBPD(x)				(((x)&0xFF)<<16)
#define S3C_VIDTCON0_VFPD(x) 				(((x)&0xFF)<<8)
#define S3C_VIDTCON0_VSPW(x) 				(((x)&0xFF)<<0)

/* VIDEO Time Control 1 register - VIDTCON1 */
#define S3C_VIDTCON1_VFPDE(x)				(((x)&0xFF)<<24)
#define S3C_VIDTCON1_HBPD(x) 				(((x)&0xFF)<<16)
#define S3C_VIDTCON1_HFPD(x) 				(((x)&0xFF)<<8)
#define S3C_VIDTCON1_HSPW(x) 				(((x)&0xFF)<<0)

/* VIDEO Time Control 2 register - VIDTCON2 */
#define S3C_VIDTCON2_LINEVAL(x)  			(((x)&0x7FF)<<11) /* these bits determine the vertical size of lcd panel */
#define S3C_VIDTCON2_HOZVAL(x)   			(((x)&0x7FF)<<0) /* these bits determine the horizontal size of lcd panel*/


/* Window 0~4 Control register - WINCONx */
#define S3C_WINCONx_WIDE_NARROW(x)			(((x)&0x3)<<26)
#define S3C_WINCONx_ENLOCAL_DMA				(0<<22)
#define S3C_WINCONx_ENLOCAL				(1<<22)
#define S3C_WINCONx_ENLOCAL_MASK			(1<<22)
#define S3C_WINCONx_BUFSEL_0				(0<<20)
#define S3C_WINCONx_BUFSEL_1				(1<<20)
#define S3C_WINCONx_BUFSEL_MASK				(1<<20)
#define S3C_WINCONx_BUFAUTOEN_DISABLE			(0<<19)
#define S3C_WINCONx_BUFAUTOEN_ENABLE			(1<<19)
#define S3C_WINCONx_BUFAUTOEN_MASK			(1<<19)
#define S3C_WINCONx_BITSWP_DISABLE			(0<<18)
#define S3C_WINCONx_BITSWP_ENABLE			(1<<18)
#define S3C_WINCONx_BYTSWP_DISABLE			(0<<17)
#define S3C_WINCONx_BYTSWP_ENABLE			(1<<17)
#define S3C_WINCONx_HAWSWP_DISABLE			(0<<16)
#define S3C_WINCONx_HAWSWP_ENABLE			(1<<16)
#define S3C_WINCONx_WSWP_DISABLE			(0<<15)
#define S3C_WINCONx_WSWP_ENABLE				(1<<15)
#define S3C_WINCONx_INRGB_RGB		   		(0<<13)
#define S3C_WINCONx_INRGB_YUV		 		(1<<13)
#define S3C_WINCONx_INRGB_MASK				(1<<13)
#define S3C_WINCONx_BURSTLEN_16WORD			(0<<9)
#define S3C_WINCONx_BURSTLEN_8WORD			(1<<9)
#define S3C_WINCONx_BURSTLEN_4WORD			(2<<9)
#define S3C_WINCONx_BLD_PIX_PLANE			(0<<6)
#define S3C_WINCONx_BLD_PIX_PIXEL			(1<<6)
#define S3C_WINCONx_BLD_PIX_MASK			(1<<6)
#define S3C_WINCONx_BPPMODE_F_1BPP			(0<<2)
#define S3C_WINCONx_BPPMODE_F_2BPP			(1<<2)
#define S3C_WINCONx_BPPMODE_F_4BPP			(2<<2)
#define S3C_WINCONx_BPPMODE_F_8BPP_PAL			(3<<2)
#define S3C_WINCONx_BPPMODE_F_8BPP_NOPAL		(4<<2)
#define S3C_WINCONx_BPPMODE_F_16BPP_565			(5<<2)
#define S3C_WINCONx_BPPMODE_F_16BPP_A555		(6<<2)
#define S3C_WINCONx_BPPMODE_F_18BPP_666			(8<<2)
#define S3C_WINCONx_BPPMODE_F_24BPP_888			(11<<2)
#define S3C_WINCONx_BPPMODE_F_24BPP_A887		(0xc<<2)
#define S3C_WINCONx_BPPMODE_F_25BPP_A888		(0xd<<2)
#define S3C_WINCONx_BPPMODE_F_28BPP_A888		(0xd<<2)
#define S3C_WINCONx_BPPMODE_F_MASK			(0xf<<2)
#define S3C_WINCONx_ALPHA_SEL_0				(0<<1)
#define S3C_WINCONx_ALPHA_SEL_1				(1<<1)
#define S3C_WINCONx_ALPHA_SEL_MASK			(1<<1)
#define S3C_WINCONx_ENWIN_F_DISABLE 			(0<<0)
#define S3C_WINCONx_ENWIN_F_ENABLE			(1<<0)

/* Window 1-2 Control register - WINCON1 */
#define S3C_WINCON1_LOCALSEL_TV				(0<<23)
#define S3C_WINCON1_LOCALSEL_CAMERA			(1<<23)
#define S3C_WINCON1_LOCALSEL_MASK			(1<<23)
#define S3C_WINCON2_LOCALSEL_TV				(0<<23)
#define S3C_WINCON2_LOCALSEL_CAMERA			(1<<23)
#define S3C_WINCON2_LOCALSEL_MASK			(1<<23)

/* Window 0~4 Position Control A register - VIDOSDxA */
#define S3C_VIDOSDxA_OSD_LTX_F(x)			(((x)&0x7FF)<<11)
#define S3C_VIDOSDxA_OSD_LTY_F(x)			(((x)&0x7FF)<<0)

/* Window 0~4 Position Control B register - VIDOSDxB */
#define S3C_VIDOSDxB_OSD_RBX_F(x)			(((x)&0x7FF)<<11)
#define S3C_VIDOSDxB_OSD_RBY_F(x)			(((x)&0x7FF)<<0)

/* Window 0 Position Control C register - VIDOSD0C */
#define  S3C_VIDOSD0C_OSDSIZE(x)			(((x)&0xFFFFFF)<<0)

/* Window 1~4 Position Control C register - VIDOSDxC */
#define S3C_VIDOSDxC_ALPHA0_R(x)			(((x)&0xF)<<20)
#define S3C_VIDOSDxC_ALPHA0_G(x)			(((x)&0xF)<<16)
#define S3C_VIDOSDxC_ALPHA0_B(x)			(((x)&0xF)<<12)
#define S3C_VIDOSDxC_ALPHA1_R(x)			(((x)&0xF)<<8)
#define S3C_VIDOSDxC_ALPHA1_G(x)			(((x)&0xF)<<4)
#define S3C_VIDOSDxC_ALPHA1_B(x)			(((x)&0xF)<<0)

/* Window 1~2 Position Control D register - VIDOSDxD */
#define  S3C_VIDOSDxD_OSDSIZE(x)			(((x)&0xFFFFFF)<<0)

/* Frame buffer Start Address register - VIDWxxADD0 */
#define S3C_VIDWxxADD0_VBANK_F(x) 			(((x)&0xFF)<<23) /* the end address of the LCD frame buffer. */
#define S3C_VIDWxxADD0_VBASEU_F(x)			(((x)&0xFFFFFF)<<0) /* Virtual screen offset size (the number of byte). */

/* Frame buffer End Address register - VIDWxxADD1 */
#define S3C_VIDWxxADD1_VBASEL_F(x) 			(((x)&0xFFFFFF)<<0)  /* the end address of the LCD frame buffer. */

/* Frame buffer Size register - VIDWxxADD2 */
#define S3C_VIDWxxADD2_OFFSIZE_F(x)  			(((x)&0x1FFF)<<13) /* Virtual screen offset size (the number of byte). */
#define S3C_VIDWxxADD2_PAGEWIDTH_F(x)			(((x)&0x1FFF)<<0) /* Virtual screen page width (the number of byte). */

/* VIDEO Interrupt Control 0 register - VIDINTCON0 */
#define S3C_VIDINTCON0_FIFOINTERVAL(x)			(((x)&0x3F)<<20)
#define S3C_VIDINTCON0_SYSMAINCON_DISABLE		(0<<19)
#define S3C_VIDINTCON0_SYSMAINCON_ENABLE		(1<<19)
#define S3C_VIDINTCON0_SYSSUBCON_DISABLE		(0<<18)
#define S3C_VIDINTCON0_SYSSUBCON_ENABLE			(1<<18)
#define S3C_VIDINTCON0_SYSIFDONE_DISABLE		(0<<17)
#define S3C_VIDINTCON0_SYSIFDONE_ENABLE			(1<<17)
#define S3C_VIDINTCON0_FRAMESEL0_BACK			(0<<15)
#define S3C_VIDINTCON0_FRAMESEL0_VSYNC 			(1<<15)
#define S3C_VIDINTCON0_FRAMESEL0_ACTIVE			(2<<15)
#define S3C_VIDINTCON0_FRAMESEL0_FRONT 			(3<<15)
#define S3C_VIDINTCON0_FRAMESEL0_MASK 			(3<<15)
#define S3C_VIDINTCON0_FRAMESEL1_NONE			(0<<13)
#define S3C_VIDINTCON0_FRAMESEL1_BACK			(1<<13)
#define S3C_VIDINTCON0_FRAMESEL1_VSYNC 			(2<<13)
#define S3C_VIDINTCON0_FRAMESEL1_FRONT 			(3<<13)
#define S3C_VIDINTCON0_INTFRMEN_DISABLE			(0<<12)
#define S3C_VIDINTCON0_INTFRMEN_ENABLE 			(1<<12)
#define S3C_VIDINTCON0_FRAMEINT_MASK			(0x1F<<12)
#define S3C_VIDINTCON0_FIFOSEL_WIN4			(1<<11)
#define S3C_VIDINTCON0_FIFOSEL_WIN3			(1<<10)
#define S3C_VIDINTCON0_FIFOSEL_WIN2			(1<<9)
#define S3C_VIDINTCON0_FIFOSEL_WIN1			(1<<6)
#define S3C_VIDINTCON0_FIFOSEL_WIN0			(1<<5)
#define S3C_VIDINTCON0_FIFOSEL_ALL			(0x73<<5)
#define S3C_VIDINTCON0_FIFOLEVEL_25			(0<<2)
#define S3C_VIDINTCON0_FIFOLEVEL_50			(1<<2)
#define S3C_VIDINTCON0_FIFOLEVEL_75			(2<<2)
#define S3C_VIDINTCON0_FIFOLEVEL_EMPTY 			(3<<2)
#define S3C_VIDINTCON0_FIFOLEVEL_FULL			(4<<2)
#define S3C_VIDINTCON0_INTFIFOEN_DISABLE		(0<<1)
#define S3C_VIDINTCON0_INTFIFOEN_ENABLE			(1<<1)
#define S3C_VIDINTCON0_INTEN_DISABLE			(0<<0)
#define S3C_VIDINTCON0_INTEN_ENABLE			(1<<0)
#define S3C_VIDINTCON0_INTEN_MASK			(1<<0)

/* VIDEO Interrupt Control 1 register - VIDINTCON1 */
#define S3C_VIDINTCON1_INTI80PEND			(0<<2)
#define S3C_VIDINTCON1_INTFRMPEND			(1<<1)
#define S3C_VIDINTCON1_INTFIFOPEND			(1<<0)

/* WIN 1~4 Color Key 0 register - WxKEYCON0 */
#define S3C_WxKEYCON0_KEYBLEN_DISABLE 			(0<<26)
#define S3C_WxKEYCON0_KEYBLEN_ENABLE			(1<<26)
#define S3C_WxKEYCON0_KEYEN_F_DISABLE 			(0<<25)
#define S3C_WxKEYCON0_KEYEN_F_ENABLE			(1<<25)
#define S3C_WxKEYCON0_DIRCON_MATCH_FG_IMAGE		(0<<24)
#define S3C_WxKEYCON0_DIRCON_MATCH_BG_IMAGE		(1<<24)
#define S3C_WxKEYCON0_COMPKEY(x)			(((x)&0xFFFFFF)<<0)

/* WIN 1~4 Color Key 1 register - WxKEYCON1 */
#define S3C_WxKEYCON1_COLVAL(x)				(((x)&0xFFFFFF)<<0)

/* Dithering Control 1 register - DITHMODE */
#define S3C_DITHMODE_RDITHPOS_8BIT			(0<<5)
#define S3C_DITHMODE_RDITHPOS_6BIT			(1<<5)
#define S3C_DITHMODE_RDITHPOS_5BIT			(2<<5)
#define S3C_DITHMODE_GDITHPOS_8BIT			(0<<3)
#define S3C_DITHMODE_GDITHPOS_6BIT			(1<<3)
#define S3C_DITHMODE_GDITHPOS_5BIT			(2<<3)
#define S3C_DITHMODE_BDITHPOS_8BIT			(0<<1)
#define S3C_DITHMODE_BDITHPOS_6BIT			(1<<1)
#define S3C_DITHMODE_BDITHPOS_5BIT			(2<<1)
#define S3C_DITHMODE_RGB_DITHPOS_MASK			(0x3f<<1)
#define S3C_DITHMODE_DITHERING_DISABLE			(0<<0)
#define S3C_DITHMODE_DITHERING_ENABLE			(1<<0)
#define S3C_DITHMODE_DITHERING_MASK			(1<<0)

/* Window 0~4 Color map register - WINxMAP */
#define S3C_WINxMAP_MAPCOLEN_F_ENABLE			(1<<24)
#define S3C_WINxMAP_MAPCOLEN_F_DISABLE			(0<<24)
#define S3C_WINxMAP_MAPCOLOR				(((x)&0xFFFFFF)<<0)

/* Window Palette Control register - WPALCON */
#define S3C_WPALCON_PALUPDATEEN				(1<<9)
#define S3C_WPALCON_W4PAL_16BIT_A	 		(1<<8)		/* A:5:5:5 */
#define S3C_WPALCON_W4PAL_16BIT	 			(0<<8)		/*  5:6:5 */
#define S3C_WPALCON_W3PAL_16BIT_A	 		(1<<7)		/* A:5:5:5 */
#define S3C_WPALCON_W3PAL_16BIT	 			(0<<7)		/*  5:6:5 */
#define S3C_WPALCON_W2PAL_16BIT_A	 		(1<<6)		/* A:5:5:5 */
#define S3C_WPALCON_W2PAL_16BIT	 			(0<<6)		/*  5:6:5 */
#define S3C_WPALCON_W1PAL_25BIT_A	 		(0<<3)		/* A:8:8:8 */
#define S3C_WPALCON_W1PAL_24BIT				(1<<3)		/*  8:8:8 */
#define S3C_WPALCON_W1PAL_19BIT_A			(2<<3)		/* A:6:6:6 */
#define S3C_WPALCON_W1PAL_18BIT_A	 		(3<<3)		/* A:6:6:5 */
#define S3C_WPALCON_W1PAL_18BIT				(4<<3)		/*  6:6:6 */
#define S3C_WPALCON_W1PAL_16BIT_A	 		(5<<3)		/* A:5:5:5 */
#define S3C_WPALCON_W1PAL_16BIT	 			(6<<3)		/*  5:6:5 */
#define S3C_WPALCON_W0PAL_25BIT_A	 		(0<<0)		/* A:8:8:8 */
#define S3C_WPALCON_W0PAL_24BIT				(1<<0)		/*  8:8:8 */
#define S3C_WPALCON_W0PAL_19BIT_A			(2<<0)		/* A:6:6:6 */
#define S3C_WPALCON_W0PAL_18BIT_A	 		(3<<0)		/* A:6:6:5 */
#define S3C_WPALCON_W0PAL_18BIT				(4<<0)		/*  6:6:6 */
#define S3C_WPALCON_W0PAL_16BIT_A	 		(5<<0)		/* A:5:5:5 */
#define S3C_WPALCON_W0PAL_16BIT	 			(6<<0)		/*  5:6:5 */

/* I80/RGB Trigger Control register - TRIGCON */
#define S3C_TRIGCON_SWFRSTATUS_REQUESTED		(1<<2)
#define S3C_TRIGCON_SWFRSTATUS_NOT_REQUESTED		(0<<2)
#define S3C_TRIGCON_SWTRGCMD				(1<<1)
#define S3C_TRIGCON_TRGMODE_ENABLE			(1<<0)
#define S3C_TRIGCON_TRGMODE_DISABLE			(0<<0)

/* LCD I80 Interface Control 0 register - I80IFCONA0 */
#define S3C_I80IFCONAx_LCD_CS_SETUP(x) 			(((x)&0xF)<<16)
#define S3C_I80IFCONAx_LCD_WR_SETUP(x) 			(((x)&0xF)<<12)
#define S3C_I80IFCONAx_LCD_WR_ACT(x)			(((x)&0xF)<<8)
#define S3C_I80IFCONAx_LCD_WR_HOLD(x)			(((x)&0xF)<<4)


/***************************************************************************/
/*HOST IF registers */
/* Host I/F A - */
#define S3C_HOSTIFB_MIFCON_INT2MSM_DIS			(0x0<<3)
#define S3C_HOSTIFB_MIFCON_INT2MSM_EN			(0x1<<3)
#define S3C_HOSTIFB_MIFCON_INT2AP_DIS			(0x0<<2)
#define S3C_HOSTIFB_MIFCON_INT2AP_EN			(0x1<<2)
#define S3C_HOSTIFB_MIFCON_WAKEUP_DIS			(0x0<<1)
#define S3C_HOSTIFB_MIFCON_WAKEUP_EN			(0x1<<1)

#define S3C_HOSTIFB_MIFPCON_SEL_VSYNC_DIR_OUT		(0x0<<5)
#define S3C_HOSTIFB_MIFPCON_SEL_VSYNC_DIR_IN		(0x1<<5)
#define S3C_HOSTIFB_MIFPCON_INT2M_LEVEL_DIS		(0x0<<4)
#define S3C_HOSTIFB_MIFPCON_INT2M_LEVEL_EN		(0x1<<4)
#define S3C_HOSTIFB_MIFPCON_SEL_NORMAL			(0x0<<3)
#define S3C_HOSTIFB_MIFPCON_SEL_BYPASS			(0x1<<3)

#define S3C_HOSTIFB_MIFPCON_SEL_RS0			0
#define S3C_HOSTIFB_MIFPCON_SEL_RS1			1
#define S3C_HOSTIFB_MIFPCON_SEL_RS2			2
#define S3C_HOSTIFB_MIFPCON_SEL_RS3			3
#define S3C_HOSTIFB_MIFPCON_SEL_RS4			4
#define S3C_HOSTIFB_MIFPCON_SEL_RS5			5
#define S3C_HOSTIFB_MIFPCON_SEL_RS6			6

#define S3C_WINCONx_ENLOCAL_POST                    	(1<<22)
#elif 0//defined(CONFIG_SMDKC110)

/* Video Main Control 0 register - VIDCON0 */
#define S5C_VIDCON0_INTERLACE_F_PROGRESSIVE		(0<<29)
#define S5C_VIDCON0_INTERLACE_F_INTERLACE		(1<<29)
#define S5C_VIDCON0_INTERLACE_F_MASK			(1<<29)
#define S5C_VIDCON0_VIDOUT(x)  				(((x)&0x7)<<26)
#define S5C_VIDCON0_VIDOUT_RGB_IF			(0<<26)
#define S5C_VIDCON0_VIDOUT_TV				(1<<26)
#define S5C_VIDCON0_VIDOUT_I80IF0			(2<<26)
#define S5C_VIDCON0_VIDOUT_I80IF1			(3<<26)
#define S5C_VIDCON0_VIDOUT_TVNRGBIF 			(4<<26)
#define S5C_VIDCON0_VIDOUT_TVNI80IF0			(6<<26)
#define S5C_VIDCON0_VIDOUT_TVNI80IF1			(7<<26)
#define S5C_VIDCON0_VIDOUT_MASK				(7<<26)
#define S5C_VIDCON0_L1_DATA16(x)  			(((x)&0x7)<<23)
#define S5C_VIDCON0_L1_DATA16_SUB_16_MODE		(0<<23)
#define S5C_VIDCON0_L1_DATA16_SUB_16PLUS2_MODE		(1<<23)
#define S5C_VIDCON0_L1_DATA16_SUB_9PLUS9_MODE 		(2<<23)
#define S5C_VIDCON0_L1_DATA16_SUB_16PLUS8_MODE		(3<<23)
#define S5C_VIDCON0_L1_DATA16_SUB_18_MODE		(4<<23)
#define S5C_VIDCON0_L0_DATA16(x)  			(((x)&0x7)<<20)
#define S5C_VIDCON0_L0_DATA16_MAIN_16_MODE		(0<<20)
#define S5C_VIDCON0_L0_DATA16_MAIN_16PLUS2_MODE		(1<<20)
#define S5C_VIDCON0_L0_DATA16_MAIN_9PLUS9_MODE		(2<<20)
#define S5C_VIDCON0_L0_DATA16_MAIN_16PLUS8_MODE		(3<<20)
#define S5C_VIDCON0_L0_DATA16_MAIN_18_MODE		(4<<20)
#define S5C_VIDCON0_RGSPSEL_PARAL_FORMAT	(0<<18)
#define S5C_VIDCON0_RGSPSEL_SERIAL_FORMAT	(1<<18)
#define S5C_VIDCON0_PNRMODE_RGB_P			(0<<17)
#define S5C_VIDCON0_PNRMODE_BGR_P			(1<<17)
#define S5C_VIDCON0_CLKVALUP_ALWAYS 			(0<<16)
#define S5C_VIDCON0_CLKVALUP_ST_FRM 			(1<<16)
#define S5C_VIDCON0_CLKVAL_F(x)				(((x)&0xFF)<<6)
#define S5C_VIDCON0_VCLKEN_ENABLE			(1<<5)
#define S5C_VIDCON0_CLKDIR_DIVIDED   			(1<<4)
#define S5C_VIDCON0_CLKDIR_DIRECTED  			(0<<4)
#define S5C_VIDCON0_CLKSEL_F_SCLK_FIMD	(1<<2)
#define S5C_VIDCON0_CLKSEL_F_HCLK	  		(0<<2)
#define S5C_VIDCON0_ENVID_ENABLE	    		(1 << 1)	/* 0:Disable 1:Enable LCD video output and logic immediatly */
#define S5C_VIDCON0_ENVID_DISABLE	    		(0 << 1)	/* 0:Disable 1:Enable LCD video output and logic immediatly */
#define S5C_VIDCON0_ENVID_F_ENABLE     			(1 << 0)	/* 0:Dis 1:Ena wait until Current frame end. */
#define S5C_VIDCON0_ENVID_F_DISABLE     		(0 << 0)	/* 0:Dis 1:Ena wait until Current frame end. */

/* Video Main Control 1 register - VIDCON1 */
#define S5C_VIDCON1_IVCLK_FALL_EDGE 			(0<<7)
#define S5C_VIDCON1_IVCLK_RISE_EDGE 			(1<<7)
#define S5C_VIDCON1_IHSYNC_NORMAL			(0<<6)
#define S5C_VIDCON1_IHSYNC_INVERT			(1<<6)
#define S5C_VIDCON1_IVSYNC_NORMAL			(0<<5)
#define S5C_VIDCON1_IVSYNC_INVERT			(1<<5)
#define S5C_VIDCON1_IVDEN_NORMAL			(0<<4)
#define S5C_VIDCON1_IVDEN_INVERT			(1<<4)

/* Video Main Control 2 register - VIDCON2 */
#define S5C_VIDCON2_EN601_DISABLE			(0<<23)
#define S5C_VIDCON2_EN601_ENABLE			(1<<23)
#define S5C_VIDCON2_EN601_MASK				(1<<23)
#define S5C_VIDCON2_TVFORMATSEL0_HARDWARE		(0<<14)
#define S5C_VIDCON2_TVFORMATSEL0_SOFTWARE		(1<<14)
#define S5C_VIDCON2_TVFORMATSEL0_MASK			(1<<14)
#define S5C_VIDCON2_TVFORMATSEL1_RGB			(0<<12)
#define S5C_VIDCON2_TVFORMATSEL1_YUV422			(1<<12)
#define S5C_VIDCON2_TVFORMATSEL1_YUV444			(2<<12)
#define S5C_VIDCON2_TVFORMATSEL1_MASK			(0x3<<12)
#define S5C_VIDCON2_ORGYUV_YCBCR			(0<<8)
#define S5C_VIDCON2_ORGYUV_CBCRY			(1<<8)
#define S5C_VIDCON2_ORGYUV_MASK				(1<<8)
#define S5C_VIDCON2_YUVORD_CBCR				(0<<7)
#define S5C_VIDCON2_YUVORD_CRCB				(1<<7)
#define S5C_VIDCON2_YUVORD_MASK				(1<<7)

/* VIDEO Time Control 0 register - VIDTCON0 */
#define S5C_VIDTCON0_VBPDE(x)				(((x)&0xFF)<<24)
#define S5C_VIDTCON0_VBPD(x)				(((x)&0xFF)<<16)
#define S5C_VIDTCON0_VFPD(x) 				(((x)&0xFF)<<8)
#define S5C_VIDTCON0_VSPW(x) 				(((x)&0xFF)<<0)

/* VIDEO Time Control 1 register - VIDTCON1 */
#define S5C_VIDTCON1_VFPDE(x)				(((x)&0xFF)<<24)
#define S5C_VIDTCON1_HBPD(x) 				(((x)&0xFF)<<16)
#define S5C_VIDTCON1_HFPD(x) 				(((x)&0xFF)<<8)
#define S5C_VIDTCON1_HSPW(x) 				(((x)&0xFF)<<0)

/* VIDEO Time Control 2 register - VIDTCON2 */
#define S5C_VIDTCON2_LINEVAL(x)  			(((x)&0x7FF)<<11) /* these bits determine the vertical size of lcd panel */
#define S5C_VIDTCON2_HOZVAL(x)   			(((x)&0x7FF)<<0) /* these bits determine the horizontal size of lcd panel*/


/* Window 0~4 Control register - WINCONx */
#define S5C_WINCONx_WIDE_NARROW(x)			(((x)&0x3)<<26)
#define S5C_WINCONx_ENLOCAL_DMA				(0<<22)
#define S5C_WINCONx_ENLOCAL				(1<<22)
#define S5C_WINCONx_ENLOCAL_MASK			(1<<22)
#define S5C_WINCONx_BUFSEL_0				(0<<20)
#define S5C_WINCONx_BUFSEL_1				(1<<20)
#define S5C_WINCONx_BUFSEL_MASK				(1<<20)
#define S5C_WINCONx_BUFAUTOEN_DISABLE			(0<<19)
#define S5C_WINCONx_BUFAUTOEN_ENABLE			(1<<19)
#define S5C_WINCONx_BUFAUTOEN_MASK			(1<<19)
#define S5C_WINCONx_BITSWP_DISABLE			(0<<18)
#define S5C_WINCONx_BITSWP_ENABLE			(1<<18)
#define S5C_WINCONx_BYTSWP_DISABLE			(0<<17)
#define S5C_WINCONx_BYTSWP_ENABLE			(1<<17)
#define S5C_WINCONx_HAWSWP_DISABLE			(0<<16)
#define S5C_WINCONx_HAWSWP_ENABLE			(1<<16)
#define S5C_WINCONx_WSWP_DISABLE			(0<<15)
#define S5C_WINCONx_WSWP_ENABLE				(1<<15)
#define S5C_WINCONx_INRGB_RGB		   		(0<<13)
#define S5C_WINCONx_INRGB_YUV		 		(1<<13)
#define S5C_WINCONx_INRGB_MASK				(1<<13)
#define S5C_WINCONx_BURSTLEN_16WORD			(0<<9)
#define S5C_WINCONx_BURSTLEN_8WORD			(1<<9)
#define S5C_WINCONx_BURSTLEN_4WORD			(2<<9)
#define S5C_WINCONx_BLD_PIX_PLANE			(0<<6)
#define S5C_WINCONx_BLD_PIX_PIXEL			(1<<6)
#define S5C_WINCONx_BLD_PIX_MASK			(1<<6)
#define S5C_WINCONx_BPPMODE_F_1BPP			(0<<2)
#define S5C_WINCONx_BPPMODE_F_2BPP			(1<<2)
#define S5C_WINCONx_BPPMODE_F_4BPP			(2<<2)
#define S5C_WINCONx_BPPMODE_F_8BPP_PAL			(3<<2)
#define S5C_WINCONx_BPPMODE_F_8BPP_NOPAL		(4<<2)
#define S5C_WINCONx_BPPMODE_F_16BPP_565			(5<<2)
#define S5C_WINCONx_BPPMODE_F_16BPP_A555		(6<<2)
#define S5C_WINCONx_BPPMODE_F_18BPP_666			(8<<2)
#define S5C_WINCONx_BPPMODE_F_24BPP_888			(11<<2)
#define S5C_WINCONx_BPPMODE_F_24BPP_A887		(0xc<<2)
#define S5C_WINCONx_BPPMODE_F_25BPP_A888		(0xd<<2)
#define S5C_WINCONx_BPPMODE_F_28BPP_A888		(0xd<<2)
#define S5C_WINCONx_BPPMODE_F_MASK			(0xf<<2)
#define S5C_WINCONx_ALPHA_SEL_0				(0<<1)
#define S5C_WINCONx_ALPHA_SEL_1				(1<<1)
#define S5C_WINCONx_ALPHA_SEL_MASK			(1<<1)
#define S5C_WINCONx_ENWIN_F_DISABLE 			(0<<0)
#define S5C_WINCONx_ENWIN_F_ENABLE			(1<<0)

/* Window 1-2 Control register - WINCON1 */
#define S5C_WINCON1_LOCALSEL_TV				(0<<23)
#define S5C_WINCON1_LOCALSEL_CAMERA			(1<<23)
#define S5C_WINCON1_LOCALSEL_MASK			(1<<23)
#define S5C_WINCON2_LOCALSEL_TV				(0<<23)
#define S5C_WINCON2_LOCALSEL_CAMERA			(1<<23)
#define S5C_WINCON2_LOCALSEL_MASK			(1<<23)

/* Window 0~4 Position Control A register - VIDOSDxA */
#define S5C_VIDOSDxA_OSD_LTX_F(x)			(((x)&0x7FF)<<11)
#define S5C_VIDOSDxA_OSD_LTY_F(x)			(((x)&0x7FF)<<0)

/* Window 0~4 Position Control B register - VIDOSDxB */
#define S5C_VIDOSDxB_OSD_RBX_F(x)			(((x)&0x7FF)<<11)
#define S5C_VIDOSDxB_OSD_RBY_F(x)			(((x)&0x7FF)<<0)

/* Window 0 Position Control C register - VIDOSD0C */
#define  S5C_VIDOSD0C_OSDSIZE(x)			(((x)&0xFFFFFF)<<0)

/* Window 1~4 Position Control C register - VIDOSDxC */
#define S5C_VIDOSDxC_ALPHA0_R(x)			(((x)&0xF)<<20)
#define S5C_VIDOSDxC_ALPHA0_G(x)			(((x)&0xF)<<16)
#define S5C_VIDOSDxC_ALPHA0_B(x)			(((x)&0xF)<<12)
#define S5C_VIDOSDxC_ALPHA1_R(x)			(((x)&0xF)<<8)
#define S5C_VIDOSDxC_ALPHA1_G(x)			(((x)&0xF)<<4)
#define S5C_VIDOSDxC_ALPHA1_B(x)			(((x)&0xF)<<0)

/* Window 1~2 Position Control D register - VIDOSDxD */
#define  S5C_VIDOSDxD_OSDSIZE(x)			(((x)&0xFFFFFF)<<0)

/* Frame buffer Start Address register - VIDWxxADD0 */
#define S5C_VIDWxxADD0_VBANK_F(x) 			(((x)&0xFF)<<23) /* the end address of the LCD frame buffer. */
#define S5C_VIDWxxADD0_VBASEU_F(x)			(((x)&0xFFFFFF)<<0) /* Virtual screen offset size (the number of byte). */

/* Frame buffer End Address register - VIDWxxADD1 */
#define S5C_VIDWxxADD1_VBASEL_F(x) 			(((x)&0xFFFFFF)<<0)  /* the end address of the LCD frame buffer. */

/* Frame buffer Size register - VIDWxxADD2 */
#define S5C_VIDWxxADD2_OFFSIZE_F(x)  			(((x)&0x1FFF)<<13) /* Virtual screen offset size (the number of byte). */
#define S5C_VIDWxxADD2_PAGEWIDTH_F(x)			(((x)&0x1FFF)<<0) /* Virtual screen page width (the number of byte). */

/* VIDEO Interrupt Control 0 register - VIDINTCON0 */
#define S5C_VIDINTCON0_FIFOINTERVAL(x)			(((x)&0x3F)<<20)
#define S5C_VIDINTCON0_SYSMAINCON_DISABLE		(0<<19)
#define S5C_VIDINTCON0_SYSMAINCON_ENABLE		(1<<19)
#define S5C_VIDINTCON0_SYSSUBCON_DISABLE		(0<<18)
#define S5C_VIDINTCON0_SYSSUBCON_ENABLE			(1<<18)
#define S5C_VIDINTCON0_SYSIFDONE_DISABLE		(0<<17)
#define S5C_VIDINTCON0_SYSIFDONE_ENABLE			(1<<17)
#define S5C_VIDINTCON0_FRAMESEL0_BACK			(0<<15)
#define S5C_VIDINTCON0_FRAMESEL0_VSYNC 			(1<<15)
#define S5C_VIDINTCON0_FRAMESEL0_ACTIVE			(2<<15)
#define S5C_VIDINTCON0_FRAMESEL0_FRONT 			(3<<15)
#define S5C_VIDINTCON0_FRAMESEL0_MASK 			(3<<15)
#define S5C_VIDINTCON0_FRAMESEL1_NONE			(0<<13)
#define S5C_VIDINTCON0_FRAMESEL1_BACK			(1<<13)
#define S5C_VIDINTCON0_FRAMESEL1_VSYNC 			(2<<13)
#define S5C_VIDINTCON0_FRAMESEL1_FRONT 			(3<<13)
#define S5C_VIDINTCON0_INTFRMEN_DISABLE			(0<<12)
#define S5C_VIDINTCON0_INTFRMEN_ENABLE 			(1<<12)
#define S5C_VIDINTCON0_FRAMEINT_MASK			(0x1F<<12)
#define S5C_VIDINTCON0_FIFOSEL_WIN4			(1<<11)
#define S5C_VIDINTCON0_FIFOSEL_WIN3			(1<<10)
#define S5C_VIDINTCON0_FIFOSEL_WIN2			(1<<9)
#define S5C_VIDINTCON0_FIFOSEL_WIN1			(1<<6)
#define S5C_VIDINTCON0_FIFOSEL_WIN0			(1<<5)
#define S5C_VIDINTCON0_FIFOSEL_ALL			(0x73<<5)
#define S5C_VIDINTCON0_FIFOLEVEL_25			(0<<2)
#define S5C_VIDINTCON0_FIFOLEVEL_50			(1<<2)
#define S5C_VIDINTCON0_FIFOLEVEL_75			(2<<2)
#define S5C_VIDINTCON0_FIFOLEVEL_EMPTY 			(3<<2)
#define S5C_VIDINTCON0_FIFOLEVEL_FULL			(4<<2)
#define S5C_VIDINTCON0_INTFIFOEN_DISABLE		(0<<1)
#define S5C_VIDINTCON0_INTFIFOEN_ENABLE			(1<<1)
#define S5C_VIDINTCON0_INTEN_DISABLE			(0<<0)
#define S5C_VIDINTCON0_INTEN_ENABLE			(1<<0)
#define S5C_VIDINTCON0_INTEN_MASK			(1<<0)

/* VIDEO Interrupt Control 1 register - VIDINTCON1 */
#define S5C_VIDINTCON1_INTI80PEND			(0<<2)
#define S5C_VIDINTCON1_INTFRMPEND			(1<<1)
#define S5C_VIDINTCON1_INTFIFOPEND			(1<<0)

/* WIN 1~4 Color Key 0 register - WxKEYCON0 */
#define S5C_WxKEYCON0_KEYBLEN_DISABLE 			(0<<26)
#define S5C_WxKEYCON0_KEYBLEN_ENABLE			(1<<26)
#define S5C_WxKEYCON0_KEYEN_F_DISABLE 			(0<<25)
#define S5C_WxKEYCON0_KEYEN_F_ENABLE			(1<<25)
#define S5C_WxKEYCON0_DIRCON_MATCH_FG_IMAGE		(0<<24)
#define S5C_WxKEYCON0_DIRCON_MATCH_BG_IMAGE		(1<<24)
#define S5C_WxKEYCON0_COMPKEY(x)			(((x)&0xFFFFFF)<<0)

/* WIN 1~4 Color Key 1 register - WxKEYCON1 */
#define S5C_WxKEYCON1_COLVAL(x)				(((x)&0xFFFFFF)<<0)

/* Dithering Control 1 register - DITHMODE */
#define S5C_DITHMODE_RDITHPOS_8BIT			(0<<5)
#define S5C_DITHMODE_RDITHPOS_6BIT			(1<<5)
#define S5C_DITHMODE_RDITHPOS_5BIT			(2<<5)
#define S5C_DITHMODE_GDITHPOS_8BIT			(0<<3)
#define S5C_DITHMODE_GDITHPOS_6BIT			(1<<3)
#define S5C_DITHMODE_GDITHPOS_5BIT			(2<<3)
#define S5C_DITHMODE_BDITHPOS_8BIT			(0<<1)
#define S5C_DITHMODE_BDITHPOS_6BIT			(1<<1)
#define S5C_DITHMODE_BDITHPOS_5BIT			(2<<1)
#define S5C_DITHMODE_RGB_DITHPOS_MASK			(0x3f<<1)
#define S5C_DITHMODE_DITHERING_DISABLE			(0<<0)
#define S5C_DITHMODE_DITHERING_ENABLE			(1<<0)
#define S5C_DITHMODE_DITHERING_MASK			(1<<0)

/* Window 0~4 Color map register - WINxMAP */
#define S5C_WINxMAP_MAPCOLEN_F_ENABLE			(1<<24)
#define S5C_WINxMAP_MAPCOLEN_F_DISABLE			(0<<24)
#define S5C_WINxMAP_MAPCOLOR				(((x)&0xFFFFFF)<<0)

/* Window Palette Control register - WPALCON */
#define S5C_WPALCON_PALUPDATEEN				(1<<9)
#define S5C_WPALCON_W4PAL_16BIT_A	 		(1<<8)		/* A:5:5:5 */
#define S5C_WPALCON_W4PAL_16BIT	 			(0<<8)		/*  5:6:5 */
#define S5C_WPALCON_W3PAL_16BIT_A	 		(1<<7)		/* A:5:5:5 */
#define S5C_WPALCON_W3PAL_16BIT	 			(0<<7)		/*  5:6:5 */
#define S5C_WPALCON_W2PAL_16BIT_A	 		(1<<6)		/* A:5:5:5 */
#define S5C_WPALCON_W2PAL_16BIT	 			(0<<6)		/*  5:6:5 */
#define S5C_WPALCON_W1PAL_25BIT_A	 		(0<<3)		/* A:8:8:8 */
#define S5C_WPALCON_W1PAL_24BIT				(1<<3)		/*  8:8:8 */
#define S5C_WPALCON_W1PAL_19BIT_A			(2<<3)		/* A:6:6:6 */
#define S5C_WPALCON_W1PAL_18BIT_A	 		(3<<3)		/* A:6:6:5 */
#define S5C_WPALCON_W1PAL_18BIT				(4<<3)		/*  6:6:6 */
#define S5C_WPALCON_W1PAL_16BIT_A	 		(5<<3)		/* A:5:5:5 */
#define S5C_WPALCON_W1PAL_16BIT	 			(6<<3)		/*  5:6:5 */
#define S5C_WPALCON_W0PAL_25BIT_A	 		(0<<0)		/* A:8:8:8 */
#define S5C_WPALCON_W0PAL_24BIT				(1<<0)		/*  8:8:8 */
#define S5C_WPALCON_W0PAL_19BIT_A			(2<<0)		/* A:6:6:6 */
#define S5C_WPALCON_W0PAL_18BIT_A	 		(3<<0)		/* A:6:6:5 */
#define S5C_WPALCON_W0PAL_18BIT				(4<<0)		/*  6:6:6 */
#define S5C_WPALCON_W0PAL_16BIT_A	 		(5<<0)		/* A:5:5:5 */
#define S5C_WPALCON_W0PAL_16BIT	 			(6<<0)		/*  5:6:5 */

/* I80/RGB Trigger Control register - TRIGCON */
#define S5C_TRIGCON_SWFRSTATUS_REQUESTED		(1<<2)
#define S5C_TRIGCON_SWFRSTATUS_NOT_REQUESTED		(0<<2)
#define S5C_TRIGCON_SWTRGCMD				(1<<1)
#define S5C_TRIGCON_TRGMODE_ENABLE			(1<<0)
#define S5C_TRIGCON_TRGMODE_DISABLE			(0<<0)

/* LCD I80 Interface Control 0 register - I80IFCONA0 */
#define S5C_I80IFCONAx_LCD_CS_SETUP(x) 			(((x)&0xF)<<16)
#define S5C_I80IFCONAx_LCD_WR_SETUP(x) 			(((x)&0xF)<<12)
#define S5C_I80IFCONAx_LCD_WR_ACT(x)			(((x)&0xF)<<8)
#define S5C_I80IFCONAx_LCD_WR_HOLD(x)			(((x)&0xF)<<4)


/***************************************************************************/
/*HOST IF registers */
/* Host I/F A - */

#define S5C_HOSTIFB_MIFCON_INT2MSM_DIS			(0x0<<3)
#define S5C_HOSTIFB_MIFCON_INT2MSM_EN			(0x1<<3)
#define S5C_HOSTIFB_MIFCON_INT2AP_DIS			(0x0<<2)
#define S5C_HOSTIFB_MIFCON_INT2AP_EN			(0x1<<2)
#define S5C_HOSTIFB_MIFCON_WAKEUP_DIS			(0x0<<1)
#define S5C_HOSTIFB_MIFCON_WAKEUP_EN			(0x1<<1)

#define S5C_HOSTIFB_MIFPCON_SEL_VSYNC_DIR_OUT		(0x0<<5)
#define S5C_HOSTIFB_MIFPCON_SEL_VSYNC_DIR_IN		(0x1<<5)
#define S5C_HOSTIFB_MIFPCON_INT2M_LEVEL_DIS		(0x0<<4)
#define S5C_HOSTIFB_MIFPCON_INT2M_LEVEL_EN		(0x1<<4)
#define S5C_HOSTIFB_MIFPCON_SEL_NORMAL			(0x0<<3)
#define S5C_HOSTIFB_MIFPCON_SEL_BYPASS			(0x1<<3)

#define S5C_HOSTIFB_MIFPCON_SEL_RS0			0
#define S5C_HOSTIFB_MIFPCON_SEL_RS1			1
#define S5C_HOSTIFB_MIFPCON_SEL_RS2			2
#define S5C_HOSTIFB_MIFPCON_SEL_RS3			3
#define S5C_HOSTIFB_MIFPCON_SEL_RS4			4
#define S5C_HOSTIFB_MIFPCON_SEL_RS5			5
#define S5C_HOSTIFB_MIFPCON_SEL_RS6			6

#define S5C_WINCONx_ENLOCAL_POST                    	(1<<22)

/* Dithering Control 1 Register - DITHMODE */
#define S5C_DITHMODE_DITHEN_DISABLE                  (0x00<<0)
#define S5C_DITHMODE_DITHEN_ENABLE                  (0x01<<0)
#define S5C_DITHMODE_B_DITHPOS_8_BIT             (0x00<<1)
#define S5C_DITHMODE_B_DITHPOS_6_BIT             (0x01<<1)
#define S5C_DITHMODE_B_DITHPOS_5_BIT             (0x10<<1)
#define S5C_DITHMODE_G_DITHPOS_8_BIT             (0x00<<3)
#define S5C_DITHMODE_G_DITHPOS_6_BIT             (0x01<<3)
#define S5C_DITHMODE_G_DITHPOS_5_BIT             (0x10<<3)
#define S5C_DITHMODE_R_DITHPOS_8_BIT             (0x00<<5)
#define S5C_DITHMODE_R_DITHPOS_6_BIT             (0x01<<5)
#define S5C_DITHMODE_R_DITHPOS_5_BIT             (0x10<<5)

/* Blending Equation Control Register - BLENDCON */
#define S5C_BLENDCON_4_BIT_ALPHA_VAL			(0<<0)
#define S5C_BLENDCON_8_BIT_ALPHA_VAL			(1<<0)

/* Specifies i80/ RGB trigger control register. - TRIGCON */
#define S5C_TRIGCON_SWTRGCMD_I80_ENABLE		(1<<1)
#define S5C_TRIGCON_TRGMODE_I80_ENABLE		(1<<0)
#define S5C_TRIGCON_TRGMODE_I80_DISABLE		(0<<0)


/*  - DISPLAY_CONTROL_REG */
#define S5C_DISPLAY_CONTROL_SET(x)		(((x)&0x03)<<0)
#elif defined(CONFIG_S5PC220)

/* Video Main Control 0 register - VIDCON0 */
#define S5C_VIDCON0_DIPI_DSI_EN		(0<<30)
#define S5C_VIDCON0_DIPI_DSI_DIS		(1<<30)
#define S5C_VIDCON0_DIPI_DSI_MASK			(1<<30)
#define S5C_VIDCON0_VIDOUT(x)  				(((x)&0x7)<<26)
#define S5C_VIDCON0_VIDOUT_RGB_IF			(0<<26)
#define S5C_VIDCON0_VIDOUT_TV				(1<<26)
#define S5C_VIDCON0_VIDOUT_I80IF0			(2<<26)
#define S5C_VIDCON0_VIDOUT_I80IF1			(3<<26)
#define S5C_VIDCON0_VIDOUT_TVNRGBIF 			(4<<26)
#define S5C_VIDCON0_VIDOUT_TVNI80IF0			(6<<26)
#define S5C_VIDCON0_VIDOUT_TVNI80IF1			(7<<26)
#define S5C_VIDCON0_VIDOUT_MASK				(7<<26)
#define S5C_VIDCON0_L1_DATA16(x)  			(((x)&0x7)<<23)
#define S5C_VIDCON0_L1_DATA16_SUB_16_MODE		(0<<23)
#define S5C_VIDCON0_L1_DATA16_SUB_16PLUS2_MODE		(1<<23)
#define S5C_VIDCON0_L1_DATA16_SUB_9PLUS9_MODE 		(2<<23)
#define S5C_VIDCON0_L1_DATA16_SUB_16PLUS8_MODE		(3<<23)
#define S5C_VIDCON0_L1_DATA16_SUB_18_MODE		(4<<23)
#define S5C_VIDCON0_L0_DATA16(x)  			(((x)&0x7)<<20)
#define S5C_VIDCON0_L0_DATA16_MAIN_16_MODE		(0<<20)
#define S5C_VIDCON0_L0_DATA16_MAIN_16PLUS2_MODE		(1<<20)
#define S5C_VIDCON0_L0_DATA16_MAIN_9PLUS9_MODE		(2<<20)
#define S5C_VIDCON0_L0_DATA16_MAIN_16PLUS8_MODE		(3<<20)
#define S5C_VIDCON0_L0_DATA16_MAIN_18_MODE		(4<<20)
#define S5C_VIDCON0_RGSPSEL_PARAL_FORMAT	(0<<18)
#define S5C_VIDCON0_RGSPSEL_SERIAL_FORMAT	(1<<18)
#define S5C_VIDCON0_PNRMODE_RGB_P			(0<<17)
#define S5C_VIDCON0_PNRMODE_BGR_P			(1<<17)
#define S5C_VIDCON0_CLKVALUP_ALWAYS 			(0<<16)
#define S5C_VIDCON0_CLKVALUP_ST_FRM 			(1<<16)
#define S5C_VIDCON0_CLKVAL_F(x)				(((x)&0xFF)<<6)
#define S5C_VIDCON0_VCLKEN_ENABLE			(1<<5)
/*
#define S5C_VIDCON0_CLKDIR_DIVIDED   			(1<<4)
#define S5C_VIDCON0_CLKDIR_DIRECTED  			(0<<4)
#define S5C_VIDCON0_CLKSEL_F_SCLK_FIMD	(1<<2)
#define S5C_VIDCON0_CLKSEL_F_HCLK	  		(0<<2)
*/
#define S5C_VIDCON0_ENVID_ENABLE	    		(1 << 1)	/* 0:Disable 1:Enable LCD video output and logic immediatly */
#define S5C_VIDCON0_ENVID_DISABLE	    		(0 << 1)	/* 0:Disable 1:Enable LCD video output and logic immediatly */
#define S5C_VIDCON0_ENVID_F_ENABLE     			(1 << 0)	/* 0:Dis 1:Ena wait until Current frame end. */
#define S5C_VIDCON0_ENVID_F_DISABLE     		(0 << 0)	/* 0:Dis 1:Ena wait until Current frame end. */

/* Video Main Control 1 register - VIDCON1 */
#define S5C_VIDVON1_FIXVCLD_HOLD		(0 << 9)
#define S5C_VIDVON1_FIXVCLD_RUNNING	(1 << 9)
#define S5C_VIDVON1_FIXVCLD_RUNNING_AND_DIS_VDEN	(2 << 9)

#define S5C_VIDCON1_IVCLK_FALL_EDGE 			(0<<7)
#define S5C_VIDCON1_IVCLK_RISE_EDGE 			(1<<7)
#define S5C_VIDCON1_IHSYNC_NORMAL			(0<<6)
#define S5C_VIDCON1_IHSYNC_INVERT			(1<<6)
#define S5C_VIDCON1_IVSYNC_NORMAL			(0<<5)
#define S5C_VIDCON1_IVSYNC_INVERT			(1<<5)
#define S5C_VIDCON1_IVDEN_NORMAL			(0<<4)
#define S5C_VIDCON1_IVDEN_INVERT			(1<<4)

/* Video Main Control 2 register - VIDCON2 */
#define S5C_VIDCON2_RGB_SKIP_EN			(1 << 27)
#define S5C_VIDCON2_RGB_SKIP_DIS			(0 << 27)
#define S5C_VIDCON2_RGB_SKIP_MASK			(1 << 27)

#define S5C_VIDCON2_RGB_DUMMY_LOC_FIRST			(1 << 25)
#define S5C_VIDCON2_RGB_DUMMY_LOC_LAST			(0 << 25)
#define S5C_VIDCON2_RGB_DUMMY_LOC_EN			(1 << 24)
#define S5C_VIDCON2_RGB_DUMMY_LOC_DIS			(0 << 24)
/*
#define S5C_VIDCON2_EN601_DISABLE			(0<<23)
#define S5C_VIDCON2_EN601_ENABLE			(1<<23)
#define S5C_VIDCON2_EN601_MASK				(1<<23)
*/
#define S5C_VIDCON2_RGB_ORDER_E(x)	(((x)&0x7)<<19)
#define S5C_VIDCON2_RGB_ORDER_O(x)	(((x)&0x7)<<16)
/*
#define S5C_VIDCON2_TVFORMATSEL0_HARDWARE		(0<<14)
#define S5C_VIDCON2_TVFORMATSEL0_SOFTWARE		(1<<14)
#define S5C_VIDCON2_TVFORMATSEL0_MASK			(1<<14)
*/
#define S5C_VIDCON2_TVFORMATSEL1_RESERVED		(0<<12)
#define S5C_VIDCON2_TVFORMATSEL1_YUV422			(1<<12)
#define S5C_VIDCON2_TVFORMATSEL1_YUV444			(2<<12)
#define S5C_VIDCON2_TVFORMATSEL1_MASK			(0x3<<12)
#define S5C_VIDCON2_ORGYUV_YCBCR			(0<<8)
#define S5C_VIDCON2_ORGYUV_CBCRY			(1<<8)
#define S5C_VIDCON2_ORGYUV_MASK				(1<<8)
#define S5C_VIDCON2_YUVORD_CBCR				(0<<7)
#define S5C_VIDCON2_YUVORD_CRCB				(1<<7)
#define S5C_VIDCON2_YUVORD_MASK				(1<<7)
#define S5C_VIDCON2_WB_FRAME_SKIP(x)	(((x)&0x1F)<<0)

/* Video Main Control 3 register - VIDCON3 */
#define S5C_VIDCON3_CG_ON_EN		(1<<18)
#define S5C_VIDCON3_CG_ON_DIS		(0<<18)
#define S5C_VIDCON3_GM_ON_EN		(1<<16)
#define S5C_VIDCON3_GM_ON_DIS		(0<<16)
#define S5C_VIDCON3_GM_MODE_64STEP		(1<<15)
#define S5C_VIDCON3_GM_MODE_16STEP		(0<<15)
#define S5C_VIDCON3_HUE_SCS_F_WIDE		(1<<14)
#define S5C_VIDCON3_HUE_SCS_F_NARROW		(0<<14)

/* VIDEO Time Control 0 register - VIDTCON0 */
#define S5C_VIDTCON0_VBPDE(x)				(((x)&0xFF)<<24)
#define S5C_VIDTCON0_VBPD(x)				(((x)&0xFF)<<16)
#define S5C_VIDTCON0_VFPD(x) 				(((x)&0xFF)<<8)
#define S5C_VIDTCON0_VSPW(x) 				(((x)&0xFF)<<0)

/* VIDEO Time Control 1 register - VIDTCON1 */
#define S5C_VIDTCON1_VFPDE(x)				(((x)&0xFF)<<24)
#define S5C_VIDTCON1_HBPD(x) 				(((x)&0xFF)<<16)
#define S5C_VIDTCON1_HFPD(x) 				(((x)&0xFF)<<8)
#define S5C_VIDTCON1_HSPW(x) 				(((x)&0xFF)<<0)

/* VIDEO Time Control 2 register - VIDTCON2 */
#define S5C_VIDTCON2_LINEVAL(x)  			(((x)&0x7FF)<<11) /* these bits determine the vertical size of lcd panel */
#define S5C_VIDTCON2_HOZVAL(x)   			(((x)&0x7FF)<<0) /* these bits determine the horizontal size of lcd panel*/


/* Window 0~4 Control register - WINCONx */
#define S5C_WINCONx_WIDE_NARROW(x)			(((x)&0x3)<<26)
#define S5C_WINCONx_ENLOCAL_DMA				(0<<22)
#define S5C_WINCONx_ENLOCAL				(1<<22)
#define S5C_WINCONx_ENLOCAL_MASK			(1<<22)
#define S5C_WINCONx_BUFSEL_0				(0<<20)
#define S5C_WINCONx_BUFSEL_1				(1<<20)
#define S5C_WINCONx_BUFSEL_MASK				(1<<20)
#define S5C_WINCONx_BUFAUTOEN_DISABLE			(0<<19)
#define S5C_WINCONx_BUFAUTOEN_ENABLE			(1<<19)
#define S5C_WINCONx_BUFAUTOEN_MASK			(1<<19)
#define S5C_WINCONx_BITSWP_DISABLE			(0<<18)
#define S5C_WINCONx_BITSWP_ENABLE			(1<<18)
#define S5C_WINCONx_BYTSWP_DISABLE			(0<<17)
#define S5C_WINCONx_BYTSWP_ENABLE			(1<<17)
#define S5C_WINCONx_HAWSWP_DISABLE			(0<<16)
#define S5C_WINCONx_HAWSWP_ENABLE			(1<<16)
#define S5C_WINCONx_WSWP_DISABLE			(0<<15)
#define S5C_WINCONx_WSWP_ENABLE				(1<<15)
#define S5C_WINCONx_INRGB_RGB		   		(0<<13)
#define S5C_WINCONx_INRGB_YUV		 		(1<<13)
#define S5C_WINCONx_INRGB_MASK				(1<<13)
#define S5C_WINCONx_BURSTLEN_16WORD			(0<<9)
#define S5C_WINCONx_BURSTLEN_8WORD			(1<<9)
#define S5C_WINCONx_BURSTLEN_4WORD			(2<<9)
#define S5C_WINCONx_BLD_PIX_PLANE			(0<<6)
#define S5C_WINCONx_BLD_PIX_PIXEL			(1<<6)
#define S5C_WINCONx_BLD_PIX_MASK			(1<<6)
#define S5C_WINCONx_BPPMODE_F_1BPP			(0<<2)
#define S5C_WINCONx_BPPMODE_F_2BPP			(1<<2)
#define S5C_WINCONx_BPPMODE_F_4BPP			(2<<2)
#define S5C_WINCONx_BPPMODE_F_8BPP_PAL			(3<<2)
#define S5C_WINCONx_BPPMODE_F_8BPP_NOPAL		(4<<2)
#define S5C_WINCONx_BPPMODE_F_16BPP_565			(5<<2)
#define S5C_WINCONx_BPPMODE_F_16BPP_A555		(6<<2)
#define S5C_WINCONx_BPPMODE_F_18BPP_666			(8<<2)
#define S5C_WINCONx_BPPMODE_F_24BPP_888			(11<<2)
#define S5C_WINCONx_BPPMODE_F_24BPP_A887		(0xc<<2)
#define S5C_WINCONx_BPPMODE_F_25BPP_A888		(0xd<<2)
#define S5C_WINCONx_BPPMODE_F_28BPP_A888		(0xd<<2)
#define S5C_WINCONx_BPPMODE_F_MASK			(0xf<<2)
#define S5C_WINCONx_ALPHA_SEL_0				(0<<1)
#define S5C_WINCONx_ALPHA_SEL_1				(1<<1)
#define S5C_WINCONx_ALPHA_SEL_MASK			(1<<1)
#define S5C_WINCONx_ENWIN_F_DISABLE 			(0<<0)
#define S5C_WINCONx_ENWIN_F_ENABLE			(1<<0)

/* Window 1-2 Control register - WINCON1 */
#define S5C_WINCON1_LOCALSEL_TV				(0<<23)
#define S5C_WINCON1_LOCALSEL_CAMERA			(1<<23)
#define S5C_WINCON1_LOCALSEL_MASK			(1<<23)
#define S5C_WINCON2_LOCALSEL_TV				(0<<23)
#define S5C_WINCON2_LOCALSEL_CAMERA			(1<<23)
#define S5C_WINCON2_LOCALSEL_MASK			(1<<23)

/* Window 0~4 Position Control A register - VIDOSDxA */
#define S5C_VIDOSDxA_OSD_LTX_F(x)			(((x)&0x7FF)<<11)
#define S5C_VIDOSDxA_OSD_LTY_F(x)			(((x)&0x7FF)<<0)

/* Window 0~4 Position Control B register - VIDOSDxB */
#define S5C_VIDOSDxB_OSD_RBX_F(x)			(((x)&0x7FF)<<11)
#define S5C_VIDOSDxB_OSD_RBY_F(x)			(((x)&0x7FF)<<0)

/* Window 0 Position Control C register - VIDOSD0C */
#define  S5C_VIDOSD0C_OSDSIZE(x)			(((x)&0xFFFFFF)<<0)

/* Window 1~4 Position Control C register - VIDOSDxC */
#define S5C_VIDOSDxC_ALPHA0_R(x)			(((x)&0xF)<<20)
#define S5C_VIDOSDxC_ALPHA0_G(x)			(((x)&0xF)<<16)
#define S5C_VIDOSDxC_ALPHA0_B(x)			(((x)&0xF)<<12)
#define S5C_VIDOSDxC_ALPHA1_R(x)			(((x)&0xF)<<8)
#define S5C_VIDOSDxC_ALPHA1_G(x)			(((x)&0xF)<<4)
#define S5C_VIDOSDxC_ALPHA1_B(x)			(((x)&0xF)<<0)

/* Window 1~2 Position Control D register - VIDOSDxD */
#define  S5C_VIDOSDxD_OSDSIZE(x)			(((x)&0xFFFFFF)<<0)

/* Frame buffer Start Address register - VIDWxxADD0 */
#define S5C_VIDWxxADD0_VBANK_F(x) 			(((x)&0xFF)<<23) /* the end address of the LCD frame buffer. */
#define S5C_VIDWxxADD0_VBASEU_F(x)			(((x)&0xFFFFFF)<<0) /* Virtual screen offset size (the number of byte). */

/* Frame buffer End Address register - VIDWxxADD1 */
#define S5C_VIDWxxADD1_VBASEL_F(x) 			(((x)&0xFFFFFF)<<0)  /* the end address of the LCD frame buffer. */

/* Frame buffer Size register - VIDWxxADD2 */
#define S5C_VIDWxxADD2_OFFSIZE_F(x)  			(((x)&0x1FFF)<<13) /* Virtual screen offset size (the number of byte). */
#define S5C_VIDWxxADD2_PAGEWIDTH_F(x)			(((x)&0x1FFF)<<0) /* Virtual screen page width (the number of byte). */

/* VIDEO Interrupt Control 0 register - VIDINTCON0 */
#define S5C_VIDINTCON0_FIFOINTERVAL(x)			(((x)&0x3F)<<20)
#define S5C_VIDINTCON0_SYSMAINCON_DISABLE		(0<<19)
#define S5C_VIDINTCON0_SYSMAINCON_ENABLE		(1<<19)
#define S5C_VIDINTCON0_SYSSUBCON_DISABLE		(0<<18)
#define S5C_VIDINTCON0_SYSSUBCON_ENABLE			(1<<18)
#define S5C_VIDINTCON0_SYSIFDONE_DISABLE		(0<<17)
#define S5C_VIDINTCON0_SYSIFDONE_ENABLE			(1<<17)
#define S5C_VIDINTCON0_FRAMESEL0_BACK			(0<<15)
#define S5C_VIDINTCON0_FRAMESEL0_VSYNC 			(1<<15)
#define S5C_VIDINTCON0_FRAMESEL0_ACTIVE			(2<<15)
#define S5C_VIDINTCON0_FRAMESEL0_FRONT 			(3<<15)
#define S5C_VIDINTCON0_FRAMESEL0_MASK 			(3<<15)
#define S5C_VIDINTCON0_FRAMESEL1_NONE			(0<<13)
#define S5C_VIDINTCON0_FRAMESEL1_BACK			(1<<13)
#define S5C_VIDINTCON0_FRAMESEL1_VSYNC 			(2<<13)
#define S5C_VIDINTCON0_FRAMESEL1_FRONT 			(3<<13)
#define S5C_VIDINTCON0_INTFRMEN_DISABLE			(0<<12)
#define S5C_VIDINTCON0_INTFRMEN_ENABLE 			(1<<12)
#define S5C_VIDINTCON0_FRAMEINT_MASK			(0x1F<<12)
#define S5C_VIDINTCON0_FIFOSEL_WIN4			(1<<11)
#define S5C_VIDINTCON0_FIFOSEL_WIN3			(1<<10)
#define S5C_VIDINTCON0_FIFOSEL_WIN2			(1<<9)
#define S5C_VIDINTCON0_FIFOSEL_WIN1			(1<<6)
#define S5C_VIDINTCON0_FIFOSEL_WIN0			(1<<5)
#define S5C_VIDINTCON0_FIFOSEL_ALL			(0x73<<5)
#define S5C_VIDINTCON0_FIFOLEVEL_25			(0<<2)
#define S5C_VIDINTCON0_FIFOLEVEL_50			(1<<2)
#define S5C_VIDINTCON0_FIFOLEVEL_75			(2<<2)
#define S5C_VIDINTCON0_FIFOLEVEL_EMPTY 			(3<<2)
#define S5C_VIDINTCON0_FIFOLEVEL_FULL			(4<<2)
#define S5C_VIDINTCON0_INTFIFOEN_DISABLE		(0<<1)
#define S5C_VIDINTCON0_INTFIFOEN_ENABLE			(1<<1)
#define S5C_VIDINTCON0_INTEN_DISABLE			(0<<0)
#define S5C_VIDINTCON0_INTEN_ENABLE			(1<<0)
#define S5C_VIDINTCON0_INTEN_MASK			(1<<0)

/* VIDEO Interrupt Control 1 register - VIDINTCON1 */
#define S5C_VIDINTCON1_INTI80PEND			(0<<2)
#define S5C_VIDINTCON1_INTFRMPEND			(1<<1)
#define S5C_VIDINTCON1_INTFIFOPEND			(1<<0)

/* WIN 1~4 Color Key 0 register - WxKEYCON0 */
#define S5C_WxKEYCON0_KEYBLEN_DISABLE 			(0<<26)
#define S5C_WxKEYCON0_KEYBLEN_ENABLE			(1<<26)
#define S5C_WxKEYCON0_KEYEN_F_DISABLE 			(0<<25)
#define S5C_WxKEYCON0_KEYEN_F_ENABLE			(1<<25)
#define S5C_WxKEYCON0_DIRCON_MATCH_FG_IMAGE		(0<<24)
#define S5C_WxKEYCON0_DIRCON_MATCH_BG_IMAGE		(1<<24)
#define S5C_WxKEYCON0_COMPKEY(x)			(((x)&0xFFFFFF)<<0)

/* WIN 1~4 Color Key 1 register - WxKEYCON1 */
#define S5C_WxKEYCON1_COLVAL(x)				(((x)&0xFFFFFF)<<0)

/* Dithering Control 1 register - DITHMODE */
#define S5C_DITHMODE_RDITHPOS_8BIT			(0<<5)
#define S5C_DITHMODE_RDITHPOS_6BIT			(1<<5)
#define S5C_DITHMODE_RDITHPOS_5BIT			(2<<5)
#define S5C_DITHMODE_GDITHPOS_8BIT			(0<<3)
#define S5C_DITHMODE_GDITHPOS_6BIT			(1<<3)
#define S5C_DITHMODE_GDITHPOS_5BIT			(2<<3)
#define S5C_DITHMODE_BDITHPOS_8BIT			(0<<1)
#define S5C_DITHMODE_BDITHPOS_6BIT			(1<<1)
#define S5C_DITHMODE_BDITHPOS_5BIT			(2<<1)
#define S5C_DITHMODE_RGB_DITHPOS_MASK			(0x3f<<1)
#define S5C_DITHMODE_DITHERING_DISABLE			(0<<0)
#define S5C_DITHMODE_DITHERING_ENABLE			(1<<0)
#define S5C_DITHMODE_DITHERING_MASK			(1<<0)

/* Window 0~4 Color map register - WINxMAP */
#define S5C_WINxMAP_MAPCOLEN_F_ENABLE			(1<<24)
#define S5C_WINxMAP_MAPCOLEN_F_DISABLE			(0<<24)
#define S5C_WINxMAP_MAPCOLOR				(((x)&0xFFFFFF)<<0)

/* Window Palette Control register - WPALCON */
#define S5C_WPALCON_PALUPDATEEN				(1<<9)
#define S5C_WPALCON_W4PAL_16BIT_A	 		(1<<8)		/* A:5:5:5 */
#define S5C_WPALCON_W4PAL_16BIT	 			(0<<8)		/*  5:6:5 */
#define S5C_WPALCON_W3PAL_16BIT_A	 		(1<<7)		/* A:5:5:5 */
#define S5C_WPALCON_W3PAL_16BIT	 			(0<<7)		/*  5:6:5 */
#define S5C_WPALCON_W2PAL_16BIT_A	 		(1<<6)		/* A:5:5:5 */
#define S5C_WPALCON_W2PAL_16BIT	 			(0<<6)		/*  5:6:5 */
#define S5C_WPALCON_W1PAL_25BIT_A	 		(0<<3)		/* A:8:8:8 */
#define S5C_WPALCON_W1PAL_24BIT				(1<<3)		/*  8:8:8 */
#define S5C_WPALCON_W1PAL_19BIT_A			(2<<3)		/* A:6:6:6 */
#define S5C_WPALCON_W1PAL_18BIT_A	 		(3<<3)		/* A:6:6:5 */
#define S5C_WPALCON_W1PAL_18BIT				(4<<3)		/*  6:6:6 */
#define S5C_WPALCON_W1PAL_16BIT_A	 		(5<<3)		/* A:5:5:5 */
#define S5C_WPALCON_W1PAL_16BIT	 			(6<<3)		/*  5:6:5 */
#define S5C_WPALCON_W0PAL_25BIT_A	 		(0<<0)		/* A:8:8:8 */
#define S5C_WPALCON_W0PAL_24BIT				(1<<0)		/*  8:8:8 */
#define S5C_WPALCON_W0PAL_19BIT_A			(2<<0)		/* A:6:6:6 */
#define S5C_WPALCON_W0PAL_18BIT_A	 		(3<<0)		/* A:6:6:5 */
#define S5C_WPALCON_W0PAL_18BIT				(4<<0)		/*  6:6:6 */
#define S5C_WPALCON_W0PAL_16BIT_A	 		(5<<0)		/* A:5:5:5 */
#define S5C_WPALCON_W0PAL_16BIT	 			(6<<0)		/*  5:6:5 */

/* I80/RGB Trigger Control register - TRIGCON */
#define S5C_TRIGCON_SWFRSTATUS_REQUESTED		(1<<2)
#define S5C_TRIGCON_SWFRSTATUS_NOT_REQUESTED		(0<<2)
#define S5C_TRIGCON_SWTRGCMD				(1<<1)
#define S5C_TRIGCON_TRGMODE_ENABLE			(1<<0)
#define S5C_TRIGCON_TRGMODE_DISABLE			(0<<0)

/* LCD I80 Interface Control 0 register - I80IFCONA0 */
#define S5C_I80IFCONAx_LCD_CS_SETUP(x) 			(((x)&0xF)<<16)
#define S5C_I80IFCONAx_LCD_WR_SETUP(x) 			(((x)&0xF)<<12)
#define S5C_I80IFCONAx_LCD_WR_ACT(x)			(((x)&0xF)<<8)
#define S5C_I80IFCONAx_LCD_WR_HOLD(x)			(((x)&0xF)<<4)


/***************************************************************************/
/*HOST IF registers */
/* Host I/F A - */

#define S5C_HOSTIFB_MIFCON_INT2MSM_DIS			(0x0<<3)
#define S5C_HOSTIFB_MIFCON_INT2MSM_EN			(0x1<<3)
#define S5C_HOSTIFB_MIFCON_INT2AP_DIS			(0x0<<2)
#define S5C_HOSTIFB_MIFCON_INT2AP_EN			(0x1<<2)
#define S5C_HOSTIFB_MIFCON_WAKEUP_DIS			(0x0<<1)
#define S5C_HOSTIFB_MIFCON_WAKEUP_EN			(0x1<<1)

#define S5C_HOSTIFB_MIFPCON_SEL_VSYNC_DIR_OUT		(0x0<<5)
#define S5C_HOSTIFB_MIFPCON_SEL_VSYNC_DIR_IN		(0x1<<5)
#define S5C_HOSTIFB_MIFPCON_INT2M_LEVEL_DIS		(0x0<<4)
#define S5C_HOSTIFB_MIFPCON_INT2M_LEVEL_EN		(0x1<<4)
#define S5C_HOSTIFB_MIFPCON_SEL_NORMAL			(0x0<<3)
#define S5C_HOSTIFB_MIFPCON_SEL_BYPASS			(0x1<<3)

#define S5C_HOSTIFB_MIFPCON_SEL_RS0			0
#define S5C_HOSTIFB_MIFPCON_SEL_RS1			1
#define S5C_HOSTIFB_MIFPCON_SEL_RS2			2
#define S5C_HOSTIFB_MIFPCON_SEL_RS3			3
#define S5C_HOSTIFB_MIFPCON_SEL_RS4			4
#define S5C_HOSTIFB_MIFPCON_SEL_RS5			5
#define S5C_HOSTIFB_MIFPCON_SEL_RS6			6

#define S5C_WINCONx_ENLOCAL_POST                    	(1<<22)

/* Dithering Control 1 Register - DITHMODE */
#define S5C_DITHMODE_DITHEN_DISABLE                  (0x00<<0)
#define S5C_DITHMODE_DITHEN_ENABLE                  (0x01<<0)
#define S5C_DITHMODE_B_DITHPOS_8_BIT             (0x00<<1)
#define S5C_DITHMODE_B_DITHPOS_6_BIT             (0x01<<1)
#define S5C_DITHMODE_B_DITHPOS_5_BIT             (0x10<<1)
#define S5C_DITHMODE_G_DITHPOS_8_BIT             (0x00<<3)
#define S5C_DITHMODE_G_DITHPOS_6_BIT             (0x01<<3)
#define S5C_DITHMODE_G_DITHPOS_5_BIT             (0x10<<3)
#define S5C_DITHMODE_R_DITHPOS_8_BIT             (0x00<<5)
#define S5C_DITHMODE_R_DITHPOS_6_BIT             (0x01<<5)
#define S5C_DITHMODE_R_DITHPOS_5_BIT             (0x10<<5)

/* Blending Equation Control Register - BLENDCON */
#define S5C_BLENDCON_4_BIT_ALPHA_VAL			(0<<0)
#define S5C_BLENDCON_8_BIT_ALPHA_VAL			(1<<0)

/* Specifies i80/ RGB trigger control register. - TRIGCON */
#define S5C_TRIGCON_SWTRGCMD_I80_ENABLE		(1<<1)
#define S5C_TRIGCON_TRGMODE_I80_ENABLE		(1<<0)
#define S5C_TRIGCON_TRGMODE_I80_DISABLE		(0<<0)


/*  - DISPLAY_CONTROL_REG */
#define S5C_DISPLAY_CONTROL_SET(x)		(((x)&0x03)<<0)


#endif

//urbetter: change to env mode
extern int FB_START_ADD;

extern int SCREEN_WIDTH;
extern int SCREEN_HEIGHT;

extern int S5C_FB_HFP;	
extern int S5C_FB_HSW;
extern int S5C_FB_HBP;
                        	
extern int S5C_FB_VFP;	
extern int S5C_FB_VSW;
extern int S5C_FB_VBP;

extern int S5C_FB_IVCLK_RISE_EDGE;



#define S5C_FB_HRES			SCREEN_WIDTH	/* horizon pixel  x resolition */
#define S5C_FB_VRES			SCREEN_HEIGHT	/* line cnt       y resolution */

#define S5C_FB_HRES_VIRTUAL	SCREEN_WIDTH		/* horizon pixel  x resolition */
#define S5C_FB_VRES_VIRTUAL	(SCREEN_HEIGHT * 2)	/* line cnt       y resolution */

#define S5C_FB_HRES_OSD		SCREEN_WIDTH	/* horizon pixel  x resolition */
#define S5C_FB_VRES_OSD		SCREEN_HEIGHT	/* line cnt       y resolution */

#if defined(CONFIG_S5PC220)

#define __REG(x)	(*(unsigned int *)(x))

//#define S5C_FB_VFRAME_FREQ     	50	/* frame rate freq */
//#define S5C_FB_PIXEL_CLOCK	(S5C_FB_VFRAME_FREQ * (S5C_FB_HFP + S5C_FB_HSW + S5C_FB_HBP + S5C_FB_HRES) * (S5C_FB_VFP + S5C_FB_VSW + S5C_FB_VBP + S5C_FB_VRES))

#define VIDCON0			__REG(0x11c00000)
#define VIDCON1			__REG(0x11c00004)
#define VIDCON2			__REG(0x11c00008)
#define VIDCON3			__REG(0x11c0000c)

#define VIDTCON0		__REG(0x11c00010)
#define VIDTCON1		__REG(0x11c00014)
#define VIDTCON2		__REG(0x11c00018)
#define VIDTCON3		__REG(0x11c0001C)

#define WINCON0			__REG(0x11c00020)
#define WINCON1			__REG(0x11c00024)
#define WINCON2			__REG(0x11c00028)
#define WINCON3 		__REG(0x11c0002C)

#define WINCON4			__REG(0x11c00030)
#define SHADOWCON		__REG(0x11c00034)
#define WINCHMAP2		__REG(0x11c00038)

#define VIDOSD0A		__REG(0x11c00040)
#define VIDOSD0B		__REG(0x11c00044)
#define VIDOSD0C		__REG(0x11c00048)

#define VIDOSD1A		__REG(0x11c00050)
#define VIDOSD1B		__REG(0x11c00054)
#define VIDOSD1C		__REG(0x11c00058)
#define VIDOSD1D		__REG(0x11c0005C)

#define VIDOSD2A		__REG(0x11c00060)
#define VIDOSD2B		__REG(0x11c00064)
#define VIDOSD2C		__REG(0x11c00068)
#define VIDOSD2D		__REG(0x11c0006C)

#define VIDOSD3A		__REG(0x11c00070)
#define VIDOSD3B		__REG(0x11c00074)
#define VIDOSD3C		__REG(0x11c00078)

#define VIDOSD4A		__REG(0x11c00080)
#define VIDOSD4B		__REG(0x11c00084)
#define VIDOSD4C		__REG(0x11c00088)

#define VIDW00ADD0B0	__REG(0x11c000A0)
#define VIDW00ADD0B1	__REG(0x11c000A4)
#define VIDW00ADD0B2	__REG(0x11c020A0)

#define VIDW01ADD0B0	__REG(0x11c000A8)
#define VIDW01ADD0B1	__REG(0x11c000AC)
#define VIDW01ADD0B2	__REG(0x11c020A8)

#define VIDW02ADD0		__REG(0x11c000B0)
#define VIDW03ADD0		__REG(0x11c000B8)
#define VIDW04ADD0		__REG(0x11c000C0)

#define VIDW00ADD1B0	__REG(0x11c000D0)
#define VIDW00ADD1B1	__REG(0x11c000D4)
#define VIDW00ADD1B2	__REG(0x11c020D0)

#define VIDW01ADD1B0	__REG(0x11c000D8)
#define VIDW01ADD1B1	__REG(0x11c000DC)
#define VIDW01ADD1B2	__REG(0xF80200D8)

#define VIDW02ADD1		__REG(0x11c000E0)
#define VIDW03ADD1		__REG(0x11c000E8)
#define VIDW04ADD1		__REG(0x11c000F0)
#define VIDW00ADD2		__REG(0x11c00100)
#define VIDW01ADD2		__REG(0x11c00104)
#define VIDW02ADD2		__REG(0x11c00108)
#define VIDW03ADD2		__REG(0x11c0010C)
#define VIDW04ADD2		__REG(0x11c00110)

#define VIDINTCON0		__REG(0x11c00130)

#define DITHMODE		__REG(0x11c00170)

#define VIDW0ALPHA0	__REG(0x11c00200)
#define VIDW0ALPHA1	__REG(0x11c00204)
#define VIDW1ALPHA0	__REG(0x11c00208)
#define VIDW1ALPHA1	__REG(0x11c0020c)
#define VIDW2ALPHA0	__REG(0x11c00210)
#define VIDW2ALPHA1	__REG(0x11c00214)
#define VIDW3ALPHA0	__REG(0x11c00218)
#define VIDW3ALPHA1	__REG(0x11c0021c)
#define VIDW4ALPHA0	__REG(0x11c00220)
#define VIDW4ALPHA1	__REG(0x11c00224)

#define BLENDCON		__REG(0x11c00260)
#define TRIGCON			__REG(0x11c001A4)

#define I80IFCONA0		__REG(0x11c001B0)
#define I80IFCONA1		__REG(0x11c001B4)
#define I80IFCONB0		__REG(0x11c001B8)
#define I80IFCONB1		__REG(0x11c001BC)

#define COLORGAINCON	__REG(0x11c001C0)

#define LDI_CMDCON0		__REG(0x11c001D0)
#define LDI_CMDCON1		__REG(0x11c001D4)

#define SIFCCON0		__REG(0x11c001E0)
#define SIFCCON1		__REG(0x11c001E4)
#define SIFCCON2		__REG(0x11c001E8)
#define HUECOEF_CR_1	__REG(0x11c001EC)

#define HUECOEF_CR_2	__REG(0x11c001F0)
#define HUECOEF_CR_3	__REG(0x11c001F4)
#define HUECOEF_CR_4	__REG(0x11c001F8)
#define HUECOEF_CB_1	__REG(0x11c001FC)

#define HUECOEF_CB_2	__REG(0x11c00200)
#define HUECOEF_CB_3	__REG(0x11c00204)

#else
#define S5C_FB_VFRAME_FREQ     	50	/* frame rate freq */

#define S5C_FB_PIXEL_CLOCK	(S5C_FB_VFRAME_FREQ * (S5C_FB_HFP + S5C_FB_HSW + S5C_FB_HBP + S5C_FB_HRES) * (S5C_FB_VFP + S5C_FB_VSW + S5C_FB_VBP + S5C_FB_VRES))

#define VIDCON0			__REG(0xF8000000)
#define VIDCON1			__REG(0xF8000004)
#define VIDCON2			__REG(0xF8000008)
#define VIDCON3			__REG(0xF800000C)

#define VIDTCON0		__REG(0xF8000010)
#define VIDTCON1		__REG(0xF8000014)
#define VIDTCON2		__REG(0xF8000018)
#define VIDTCON3		__REG(0xF800001C)

#define WINCON0			__REG(0xF8000020)
#define WINCON1			__REG(0xF8000024)
#define WINCON2			__REG(0xF8000028)
#define WINCON3 		__REG(0xF800002C)
#define WINCON4			__REG(0xF8000030)
#define SHADOWCON		__REG(0xF8000034)

#define VIDOSD0A		__REG(0xF8000040)
#define VIDOSD0B		__REG(0xF8000044)
#define VIDOSD0C		__REG(0xF8000048)

#define VIDOSD1A		__REG(0xF8000050)
#define VIDOSD1B		__REG(0xF8000054)
#define VIDOSD1C		__REG(0xF8000058)
#define VIDOSD1D		__REG(0xF800005C)

#define VIDOSD2A		__REG(0xF8000060)
#define VIDOSD2B		__REG(0xF8000064)
#define VIDOSD2C		__REG(0xF8000068)
#define VIDOSD2D		__REG(0xF800006C)

#define VIDOSD3A		__REG(0xF8000070)
#define VIDOSD3B		__REG(0xF8000074)
#define VIDOSD3C		__REG(0xF8000078)

#define VIDOSD4A		__REG(0xF8000080)
#define VIDOSD4B		__REG(0xF8000084)
#define VIDOSD4C		__REG(0xF8000088)

#define VIDW00ADD0B0	__REG(0xF80000A0)
#define VIDW00ADD0B1	__REG(0xF80000A4)
#define VIDW00ADD0B2	__REG(0xF80020A0)

#define VIDW01ADD0B0	__REG(0xF80000A8)
#define VIDW01ADD0B1	__REG(0xF80000AC)
#define VIDW01ADD0B2	__REG(0xF80020A8)

#define VIDW02ADD0		__REG(0xF80000B0)
#define VIDW03ADD0		__REG(0xF80000B8)
#define VIDW04ADD0		__REG(0xF80000C0)

#define VIDW00ADD1B0	__REG(0xF80000D0)
#define VIDW00ADD1B1	__REG(0xF80000D4)
#define VIDW00ADD1B2	__REG(0xF80020D0)

#define VIDW01ADD1B0	__REG(0xF80000D8)
#define VIDW01ADD1B1	__REG(0xF80000DC)
#define VIDW01ADD1B2	__REG(0xF80200D8)


#define VIDW02ADD1		__REG(0xF80000E0)
#define VIDW03ADD1		__REG(0xF80000E8)
#define VIDW04ADD1		__REG(0xF80000F0)
#define VIDW00ADD2		__REG(0xF8000100)
#define VIDW01ADD2		__REG(0xF8000104)
#define VIDW02ADD2		__REG(0xF8000108)
#define VIDW03ADD2		__REG(0xF800010C)
#define VIDW04ADD2		__REG(0xF8000110)

#define VIDINTCON0		__REG(0xF8000130)

#define DITHMODE		__REG(0xF8000170)

#define VIDW0ALPHA0	__REG(0xF8000200)
#define VIDW0ALPHA1	__REG(0xF8000204)
#define VIDW1ALPHA0	__REG(0xF8000208)
#define VIDW1ALPHA1	__REG(0xF800020c)
#define VIDW2ALPHA0	__REG(0xF8000210)
#define VIDW2ALPHA1	__REG(0xF8000214)
#define VIDW3ALPHA0	__REG(0xF8000218)
#define VIDW3ALPHA1	__REG(0xF800021c)
#define VIDW4ALPHA0	__REG(0xF8000220)
#define VIDW4ALPHA1	__REG(0xF8000224)

#define BLENDCON		__REG(0xF8000260)
#define TRIGCON			__REG(0xF80001A4)
#endif

#define mv_RGB_FORMAT_555  555
#define mv_RGB_FORMAT_565  565
#define mv_RGB_FORMAT_888  888
#define mv_RGB_FORMAT_666  666

//change this line if you are using other rgb format
#ifdef CONFIG_LCD_COLOR_RGB888
#define mv_RGB_FORMAT mv_RGB_FORMAT_888
#else
#define mv_RGB_FORMAT mv_RGB_FORMAT_565
#endif

#if ( mv_RGB_FORMAT == mv_RGB_FORMAT_565)
    typedef unsigned short  mv_color;
    #define mv_RGB2Color(r, g, b)  (mv_color)(((r) >> 3) << 11 | ((g) >> 2) << 5 | ((b) >> 3))
#elif ( mv_RGB_FORMAT == mv_RGB_FORMAT_555)
    typedef unsigned short  mv_color;
    #define mv_RGB2Color(r, g, b)  (mv_color)(((r) >> 3) << 10 | ((g) >> 3) << 5 | ((b) >> 3) & 0x7fff)

#elif ( mv_RGB_FORMAT == mv_RGB_FORMAT_888)
    typedef unsigned int mv_color;
    #define mv_RGB2Color(r, g, b)   (mv_color)(((r) << 16 | (g) << 8 | (b)) & 0x00FFFFFF)

#elif ( mv_RGB_FORMAT == mv_RGB_FORMAT_666)
    typedef unsigned int mv_color;
    #define mv_RGB2Color(r, g, b)  (mv_color)(((r) >> 2) << 12 | ((g) >> 2) << 6 | ((b) >> 2))
#else
    #error "unknown rgb format."
#endif


typedef struct
{
    int     width;
    int     height;
    int     lineBytes;
    char *  startAddr;
}mv_surface;

typedef struct tag_bmp_file_header
{ // bmfh
        unsigned short bfType;	
        unsigned long bfSize; 
        unsigned long bfReserved; 
        unsigned long bfOffBits;

        unsigned long biSize; 
        long int biWidth; 
        long int biHeight; 
        unsigned short biPlanes; 
        unsigned short biBitCount; 
        unsigned long biCompression; 
        unsigned long biSizeImage; 
        long int biXPelsPerMeter; 
        long int biYPelsPerMeter; 
        unsigned long biClrUsed; 
        unsigned long biClrImportant;
}__attribute__ ((packed)) bmp_info_header;


//#define SCREEN_WIDTH	1024
//#define SCREEN_HEIGHT    768
//#define SCREEN_MEM_SIZE		(SCREEN_WIDTH*SCREEN_HEIGHT*4)

//extern int SCREEN_WIDTH;
//extern int SCREEN_HEIGHT;

#define SCREEN_MEM_SIZE		((SCREEN_WIDTH*SCREEN_HEIGHT)*4)
void ut_update_lcd_param();

//void s5p_lcdc_init(void);
void LCD_turnon(void);
void LCD_setfgcolor(unsigned int color);
void LCD_setleftcolor(unsigned int color);
void LCD_setprogress(int percentage);
void LCD_display_pic(int type);


#endif /*__S5P_LCD_H__*/
